This invention relates to semiconductor memory devices, and more particularly to a method of recovering overerased bits in memory devices.
In conventional single bit per cell memory devices, the memory cell assumes one of two information storage states, either an on-state or an off-state. This combination of either on or off defines one bit of information. In bi-level memories, since the cells can only have two different values of threshold voltage, Vt, during the reading operation, it is only necessary to sense whether or not the addressed transistor is conductive. This is generally done by comparing the current flowing through the memory transistor biased with predetermined drain-to-source and gate-to-source voltages with that of a reference transistor under the same bias conditions, either directly through current-mode sensing or after a current-to-voltage conversion through voltage-mode sensing.
In programming a typical single-bit-per-cell flash memory cell, a high potential (such as, for example, approximately 9-12 volts) is applied to the control gate of the cell, the source terminal is grounded, and the drain terminal is connected to a voltage of about 5 volts. This operation can be performed in an array by selectively applying the pulse to the word line which connects the control gates, and biasing the bit line which connects the drains. This is commonly known in the art as the hot electron injection method of programming flash memory cells. Hot electron injection is used to move charge in the floating gate, thus changing the threshold voltage of the floating gate transistor. By placing the high voltage on the control gate, this generates electrons to flow in the channel and some hot electrons are injected on to the floating gate and change the potential of the floating gate to be more negative. Therefore, injection tends to saturate and the threshold voltage of a floating gate transistor follows the same trend. The state of the memory cell transistor is read or sensed by placing an operating voltage (for example, approximately 4-6 volts) on its control gate and 0.5-1 volts on the drain, and then detecting the level of current flowing between the source and drain to determine which memory state the cell is in.
Programming and,sensing schemes for multi-level memory devices are more complex, typically requiring 2nxe2x88x921 voltage references, where n is the number of bits stored in the cell. With reference to FIG. 9, an example of a prior art multi-level memory device is shown having two bits per cell which corresponds to four memory levels having three voltage references. A first memory level 121, represented by the binary number 11, is the state in which the memory cell has no charge. The memory level 124 in which the memory cell is fully charged is represented by the binary number 00. (The terms xe2x80x9cno chargexe2x80x9d and xe2x80x9cfully chargedxe2x80x9d are used herein, and throughout this discussion, for the purposes of explanation and are not intended to be limiting. For example, the (11) state could have a slight amount of charge and the (00) state could have an amount of charge less than the absolute maximum amount of charge.) In between the uncharged state (11) 121 and the fully charged state (00) 124 are a first intermediate level 122, represented by the binary number 10, in which the memory cell has a small amount of charge, and a second intermediate level 123, represented by the binary number 01, in which the memory cell has more charge than the 10 state but is not fully charged. The threshold voltages (Vt) shown in between each of the memory states of the memory cell represent the threshold voltages needed to transition between memory cell states. As discussed, for a two-bit cell having four memory levels, there are three voltage references 111, 112, 113. For example, at the threshold voltage of 2.5 volts, the memory state is at the reference level 111 where the state of the cell will transition from the 11 state to the 10 state. At a voltage threshold Vt=3.5 volts, the memory cell is at the reference level 112 where the state of the cell will transition from the 10 state to the 01 state. And at the voltage threshold of Vt=4.5 volts, the memory cell is at the reference level 113 where the state of the cell will transition from the 01 state to the 00 state. The threshold voltage values shown in FIG. 9 are merely illustrative and the actual values of Vt will depend on the construction of the memory cell.
One of the main difficulties in implementing multi-level nonvolatile memory cells is being able to accurately program the cell, i.e. to place just the amount of charge on the floating gate of the cell transistor that is required to obtain the target value of the threshold voltage. The usual manner that is used in the prior art to deal with the problem of accurate charge placement is by using a cell-by-cell program and verify approach. In the program and verify approach, the programming operation is divided into a number of partial steps and the cell is sensed after every step to determine whether or not the target threshold voltage is achieved, so as to continue the programming if this is not the case. As each cell is independently controlled during programming, this technique allows simultaneous programming of a whole byte or even a number of bytes. This procedure ensures that the target Vt is reached, with the accuracy allowed by the quantization inherent in the use of finite programming steps. However, this process can be very long and must be controlled by on-chip logic circuitry.
A typical program and verify technique is illustrated in FIG. 10. As shown in FIG. 10, the programming of the memory cell is implemented by an alternating sequence of programming and verifying voltage pulses. The voltage 130 of each programming pulse incrementally increases with respect to time 132 until the desired target voltage is reached. The voltage level of the verify pulse remains constant throughout the programming process. For example as shown, after a first verify pulse 151, a first programming pulse 141 is implemented, and then a verify pulse 152 follows. A next programming pulse 142 of an incrementally increased potential is applied, followed by a verify pulse 153, followed by a third programming pulse 143 which is increased in voltage from the previous programming step, followed by a next verify pulse 154 and so on, until the final programming pulse 147 is applied to allow the cell to reach the threshold voltage of the desired memory state. As can be seen in FIG. 10, the shape of the graph resembles a staircase, and this programming method is generally known in the art as staircase gate voltage ramp programming. This staircase method is described in numerous patents, including, for example, U.S. Pat. Nos. 5,043,940; 5,268,870; 5,293,560; and 5,434,825.
The electrical erase of a flash memory cell is usually a global operation that is applied to entire sections of a memory array. Each sector has its own internal source line and its own circuitry used to switch this line. To perform the erase, a high electric field is provided between the source and the floating gate of the cell, causing the extraction of negative charge from the floating gate by means of Fowler-Nordheim tunneling. Typically, the erase operation is accomplished by placing a large negative voltage, such as xe2x88x9210V, on the floating gate and a positive voltage, such as 6V on the source.
FIG. 11 illustrates the ideal threshold voltage distribution for a multi-level memory device. The Vt distribution for each memory level is in the typical bell-shaped curve, with greatest number of cells at the target Vt at the center of the cell distribution curve and the number of cells decreasing as the voltage moves away, on both sides, from the target Vt. The cell distribution curves 172, 173, 174 for the states 10, 01 and 00 are similar to each other and are much tighter than the curve 171 for the 11 state. This is because the curve 171 for the 11 state is created by the erase mechanism, since the 11 state is the erased state, while the other states 10, 0100 are created by the programming algorithm. This Vt distribution is similar for single-bit memory devices, except that there is one erased state and only one programming state.
One of the problems in erasing flash memory cells is the fact that the cell current distribution is not consistent. Not every memory cell erases at the same threshold voltage due to variations in oxide thicknesses, the location of the die in relation to the center of the wafer, and other such factors. Therefore, because some memory cells are erased faster than others, the memory cells that become erased more quickly can become overerased. This is because the erase mechanism in flash memories does not stop by itself; as long as the erasing voltage is applied to the memory cell, electrons are continuously removed from the floating gate and the erasing pulse is not stopped at the right time. Since the erase operation continues until all of the memory cells in the sector being erased have been erased, some of the memory cells will be overerased.
FIG. 12 illustrates this concept of overerased bits. Cell distribution curve 171 represents an ideal curve in which the target threshold voltage 186 (or the threshold voltage at which most of the cells end up following the erase operation) is 2V. The undererase threshold voltage 185, or the maximum threshold voltage at which a cell is considered to be erased, is shown to be 2.5 volts. The overerase threshold voltage 184 is shown to be 1.5 volts. As explained above, it is difficult to control the cell distribution when erasing a large array of memory cells. Often times, the distribution curve would be more like curve 181. In this case, a number of memory cells 183 have been overerased due to the cells having been erased faster than other memory cells in the array. Because the erase mechanism operates until the last memory cell in the array is erased to beyond the undererase threshold 185, the faster cells 183 become overerased.
Overerasing of the memory cells is not desirable and can be a potential cause of failure because the memory array cannot be read correctly if it contains depleted cells, as all of the cells connected to the same bitline of a depleted cell would be read as a xe2x80x9c1xe2x80x9d, regardless of the actual content of the cell.
In the prior art, different soft-programming techniques have been developed to solve the problem by recovering overerased bits. For example, a small constant voltage can be applied on the wordline, such as for example 1.5V, and then a soft-programming operation can be done to program cells below 1.5V back up to the overerase threshold. However, all of the proposed soft-programming recovery techniques are time and power consuming, which is undesirable. Other techniques for recovering overerased bits involve generating a separate reference current. This is also not desirable because it does not use the existing reference cell and thus adds more complexity and power consumption.
It is the object of the present invention to provide a method of recovering the overerased bits in a memory cell which does not require soft-programming techniques and does not require the generation of a separate reference current.
It is a further object of the invention to provide a method of recovering the overerased bits in a memory cell which is faster and consumes less power.
The above objects have been achieved by a method of recovering overerased bits in a memory device, in particular a multi-level memory device, in which a pair of reference currents are generated internally to define a current window corresponding to the erased or xe2x80x9c11xe2x80x9d state. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in the memory array have an amount of charge on its floating gate that corresponds to a conduction current that is greater than the first reference current. This group of memory cells is in an overerased state. Then, a plurality of alternating programming and verifying pulses are applied to each of the group of overerased memory cells in order to program the overerased cells to the erased state. The programming pulses are at the same voltage levels as is used to program the memory cells to the other memory states (such as xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c00xe2x80x9d). Therefore, the method uses the existing programming approach and programs the xe2x80x9c11xe2x80x9d state in the same manner as the other memory states. This results in a fast and more precise recovery of overerased bits. The method also does not require soft-programming or the generation of separate reference currents, which helps to conserve power and to simplify the process.